1. Field of the Invention
The present invention relates to a method for producing a semiconductor device and a semiconductor device.
2. Description of the Related Art
The degree of integration of semiconductor integrated circuits, in particular, integrated circuits using MOS transistors has been increasing. With the increasing degree of integration, the size of MOS transistors used in integrated circuits has been decreased to nano-scale dimensions. Such a decrease in the size of MOS transistors causes difficulty in suppressing leak currents, which poses a problem in that it is hard to reduce the area occupied by the circuits because of the requirements of the secure retention of necessary currents. To address the problem, a surrounding gate transistor (hereinafter referred to as an “SGT”) having a structure in which a source, a gate, and a drain are arranged vertically with respect to a substrate and a gate electrode surrounds a pillar-shaped semiconductor layer has been proposed (e.g., refer to Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
In known inverters that use an SGT, a single transistor is formed in a single silicon pillar, and an nMOS transistor constituted by a single silicon pillar and a pMOS transistor constituted by a single silicon pillar are formed on a plane (e.g., refer to Japanese Unexamined Patent Application Publication No. 2008-300558). Since at least two silicon pillars are formed on a plane, an area corresponding to the at least two silicon pillars is required.
In known nonvolatile memories, a plurality of gates are formed in a single silicon pillar (e.g., refer to Japanese Unexamined Patent Application Publication No. 2014-57068). A gate insulating film is formed on a sidewall of the silicon pillar, and a source line and a bit line are connected to an upper end and a lower end of the silicon pillar, respectively.